PIC18F4539T-I/ML【PDF 97/322 页】IC MCU FLASH 12KX16 EE A/D 44QFN

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PIC18FXX39

DS30485A-page 184

Preliminary

2002 Microchip Technology Inc.

The value that is in the ADRESH/ADRESL registers is

not modified for a Power-on Reset. The ADRESH/

ADRESL registers will contain unknown data after a

Power-on Reset.

After the A/D module has been configured as desired,

the selected channel must be acquired before the con-

version is started. The analog input channels must

have their corresponding TRIS bits selected as an

input. To determine acquisition time, see Section 18.1.

After this acquisition time has elapsed, the A/D conver-

sion can be started. The following steps should be

followed for doing an A/D conversion:

Configure the A/D module:

Configure analog pins, voltage reference and

digital I/O (ADCON1)

Select A/D input channel (ADCON0)

Select A/D conversion clock (ADCON0)

Turn on A/D module (ADCON0)

Configure A/D interrupt (if desired):

Clear ADIF bit

Set ADIE bit

Set GIE bit

Set PEIE bit

Wait the required acquisition time.

Start conversion:

Set GO/DONE bit (ADCON0)

Wait for A/D conversion to complete, by either:

Polling for the GO/DONE bit to be cleared

(interrupts disabled)

Waiting for the A/D interrupt

Read A/D Result registers (ADRESH/ADRESL);

clear bit ADIF if required.

For next conversion, go to step 1 or step 2 as

required. The A/D conversion time per bit is

defined as TAD. A minimum wait of 2 TAD is

required before the next acquisition starts.

18.1

A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 18-2. The

source impedance (RS) and the internal sampling

switch (RSS) impedance directly affect the time

required to charge the capacitor CHOLD. The sampling

switch (RSS) impedance varies over the device voltage

(VDD). The source impedance affects the offset voltage

at the analog input (due to pin leakage current). The

maximum recommended impedance for analog

sources is 2.5 k

. After the analog input channel is

selected (changed), this acquisition must be done

before the conversion can be started.

FIGURE 18-2:

ANALOG INPUT MODEL

Note:

When the conversion is started, the hold-

ing capacitor is disconnected from the

input pin.

VAIN

CPIN

ANx

5 pF

VDD

VT = 0.6V

I LEAKAGE

RIC

≤ 1k

Sampling

Switch

RSS

CHOLD = 120 pF

VSS

Sampling Switch

56 7 8 9 10 11

)

VDD

± 500 nA

Legend: CPIN

I LEAKAGE

RIC

CHOLD

= input capacitance

= threshold voltage

= leakage current at the pin due to

= interconnect resistance

= sampling switch

= sample/hold capacitance (from DAC)

various junctions

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